1. Field of the Invention
The present invention relates to a processor apparatus and a computer system equipped with such a processor apparatus, and more particularly relates to a technique to improve instruction utilization of an instruction in a single operation processing mode, in which a coprocessor is not run in parallel in a parallel processor including a plurality of processors and thereby being capable of processing a plurality of operations in one clock cycle.
2. Background Art
Conventionally, a multiple parallel processor which carries out a plurality of operation instructions in one clock cycle has been put into practical use. FIG. 1 is a block diagram schematically showing an arrangement of such a multiple parallel processor. A processor apparatus 20 comprises an integer processor 1 which chiefly controls data transfer from a memory and an execution flow, and one or more than one data processor 2 which chiefly carries out data processing defined by an extended instruction. The integer processor 1 chiefly carries out an addition/subtraction instruction, a branch instruction, a load instruction into a data memory, data read/write instructions, etc. On the other hand, the data processor 2 carries out data processing including, for example, an arithmetic operation defined by an extended instruction, such as an SIMD (Single Instruction stream Multiple Data stream), in parallel with the integer processor 1.
By operating the integer processor 1 and data processor 2 concurrently, two or more operation instructions can be carried out simultaneously in parallel in one clock cycle.
The instruction format that operates the processor apparatus 20 comprises, as shown in FIG. 2 for example, an instruction portion 71 that defines an operation of the integer processor 1, and another instruction portion 72 that defines an operation of the data processor 2. Each of these instructions 71 and 72 comprises a 32-bit instruction, for example.
However, the conventional multiple parallel processor apparatus 20 has the following problems. That is, an instruction string of a program to be carried out by the processor apparatus 20 includes a great number of instructions that define a single operation processing, by which the integer processor 1 alone is run even for an extended instruction. For an instruction format corresponding to such a single operation processing, the conventional processor apparatus 20 has to embed an instruction not to run any unit (no operation instruction: NOP instruction) into the portion 72 that defines an operation of the data processor 2 in the instruction format shown in FIG. 2. Consequently, utilization of instructions, especially extended instructions, is reduced, and a capacity of an instruction memory for storing instructions is undesirably increased.